|
171 |
Design and Implementation of a Physically Secure Open-Source FPGA and Toolchain
Enthalten in IACR transactions on cryptographic hardware and embedded systems Bd. 2025, 2025, Nr. 3
|
|
|
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172 |
HCTR+: An Optimally Secure TBC-Based Accordion Mode
Enthalten in IACR transactions on symmetric cryptology Bd. 2025, 2025, Nr. 3
|
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173 |
HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction
Enthalten in IACR transactions on cryptographic hardware and embedded systems Bd. 2025, 2025, Nr. 3
|
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|
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174 |
KeyVisor – A Lightweight ISA Extension for Protected Key Handles with CPU-enforced Usage Policies
Enthalten in IACR transactions on cryptographic hardware and embedded systems Bd. 2025, 2025, Nr. 3
|
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175 |
LEAP: High-Performance Lattice-Based Pseudorandom Number Generator
Enthalten in IACR transactions on symmetric cryptology Bd. 2025, 2025, Nr. 3
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176 |
Minimized PRFs from Public Permutations
Enthalten in IACR transactions on symmetric cryptology Bd. 2025, 2025, Nr. 3
|
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177 |
Multidimensional Linear Cryptanalysis of AEGIS
Enthalten in IACR transactions on symmetric cryptology Bd. 2025, 2025, Nr. 3
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178 |
On the Average Random Probing Model
Enthalten in IACR transactions on cryptographic hardware and embedded systems Bd. 2025, 2025, Nr. 3
|
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179 |
On the Characterization of Phase Noise for the Robust and Resilient PLL-TRNG Design
Enthalten in IACR transactions on cryptographic hardware and embedded systems Bd. 2025, 2025, Nr. 3
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180 |
POTA: A Pipelined Oblivious Transfer Acceleration Architecture for Secure Multi-Party Computation
Enthalten in IACR transactions on cryptographic hardware and embedded systems Bd. 2025, 2025, Nr. 3
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Administration
